1. Field of the Invention
The invention relates generally to a method of manufacturing integrated circuit (hereinafter referred to as "IC") devices and, more particularly, relates to a method of manufacturing IC devices including a process of forming bumps which are mainly formed along the neighborhood of the periphery of an IC chip as terminals for interconnection with external electrode terminals.
2. Description of the Background Art
As the integration density of IC devices has been increased in recent years, a pitch in the arrangement of electrode pads for interconnection with external terminals has become smaller, i.e., on the order of 100.mu.m. Accordingly, interconnection by conventional wire bonding has become difficult, so that a system is presently employed in which bumps are formed on electrode pads in advance and a lead connection terminal is bonded to the same.
Firstly, a description will now be made of an outline of a process of manufacturing IC devices with bumps as terminals to which the present invention is applied, taking a case as an example where a process of inner lead bonding by TAB (Tape Automated Bonding) assembly process is included, with reference to FIGS. 1A to 1C. Firstly, a plurality of IC chips 2 are formed on a semiconductor substrate wafer 1 in a wafer process shown in FIG. 1A. Then, as shown in FIG. 1B, bumps 3 are formed on electrode pads to be input/output terminals of the IC circuits arranged along the neighborhood of periphery of each IC chip 2. Next, finished IC chips 2 are disconnected and separated one by one. Referring to FIG. 1C, the disconnected and separated IC chips 2 are bonded to the terminals arranged inside inner leads 5 carried by a tape carrier 4 at bumps 3.
FIGS. 2A to 2C show the processes performed until one IC chip 2 is bonded with inner leads.
The IC devices with bumps formed by the processes as stated above are used for a wide variety of purposes such as a so-called gate array IC.
A process of forming bumps in a conventional method of manufacturing IC devices will now be described with reference to FIGS. 3A to 3E. Firstly, a protective film 12 is formed by CVD including SiO.sub.2 or Si.sub.3 N.sub.4 by exposing the neighborhood of the center of the surface of an electrode pad 13 on a semiconductor substrate 11 with an IC formed thereon. Thereafter, a metal layer 15 including a conductive metal is formed over the entire surface of semiconductor substrate 11, having a thickness of several thousand .ANG. to 1.mu.m (see FIG. 3A). Then, an opening is made only in the region on metal layer 15 where the bumps are to be formed, and a resist 16a is formed by lithography (see FIG. 3B).
Then, a bump 17 is formed within the opening of resist 16a by electroplating (see FIG. 3C), and thereafter, resist 16a is removed (see FIG. 3D). Then, metal layer 15 is etched using bump 17 as a mask (see FIG. 3E).
Though metal layer 15 is formed as a single layer in some cases, normally, it has a multilayer structure employing, as a bottom layer, a material having a strong adhesion with an aluminum pad 13 and, as the top layer, a material having a strong adhesion with bump 17.
Gold, for example, is employed as the material of bump 17. The reason why solder, which has been often used as a material for the bump, is not used is as follows. One method of forming solder bumps is to dip the semiconductor substrate 11 in a solder bath after patterning metal layer 15. The other method is to form a resist mask where an opening is formed only in the region in which the bumps are to be formed, on metal layer 15 formed over the entire surface of semiconductor substrate 11 and to deposit solder within this opening. In the former method in which the semiconductor substrate is dipped in the solder bath, as shown in FIG. 4, the upper portion of a formed solder bump 27 takes a big swollen shape. As for the arrangement of aluminum pad 13, as the integration density of the IC becomes higher, as shown in FIG. 10, the pitch p becomes, for example, 100.mu.m, and the distance g becomes smaller, i.e., about 30.mu.m. In this case, if the upper portion thereof becomes swollen like solder bump 27 in FIG. 4, adjacent solder bumps 27 come in contact with each other. Additionally, it becomes necessary to pattern metal layer 15 before forming the bump, therefore requiring a photolithography process for the resist mask for that reason. According to the latter method, formation is carried out in the same processes as those shown in FIGS. 3A to 3D stated above before the etching process for metal layer 15. However, as solder is inferior with respect to an etching-resistant property, if metal layer 15 is to be etched using solder bump 37 as a mask, solder bump 37 is also etched. Accordingly, the etching process for metal layer 15 required an extremely difficult process in which the outer surface of solder bump 37 was covered with a resist mask, making its practical application impossible.
Accordingly, it was indispensable to apply the method of forming the bumps by electroplating shown in FIGS. 3A to 3E.
According to the above-mentioned conventional method of forming bumps by electroplating, however, in removing, by etching, metal layer 15 outside the region where bump 17 was to be formed, metal layer 15 immediately below bump 17 was also etched by overetching as indicated by the arrow A in FIG. 3E, so that, in some cases, the adhesion strength of bump 17 was decreased, corrosion of aluminum pad 13 was caused by the etchant, or an etching residue of metal layer 15 was caused in a region other than the region where the bump 17 was to be formed. As a result, a conduction failure and peeling between bump 17 and aluminum pad 13 or an insulation failure of the IC was caused.